Memory system with dynamic calibration using a trim management mechanism
US10566063B2 · kind B2 · utility
13Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | May 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: determine a set of read results based on reading a subset of memory cells according to read levels maintained within optimization trim data, wherein the optimization trim data initially comprises at least one read level in addition to a target trim; calibrate the set of read levels based on the set of read results; and remove the calibrated read levels from the optimization trim data when the calibrated read levels satisfy a calibration condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.