Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices
US10566246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Aug 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods are provided for fabricating shared contact trenches for source/drain layers of n-type and p-type field-effect transistor devices, wherein the shared contact trenches include dual silicide layers and dual epitaxial layers. For example, a semiconductor device includes first and second field-effect transistor devices having respective first and second source/drain layers, and a shared contact trench, wherein the first and second source/drain layers are disposed adjacent to each other within the shared contact trench, and are commonly connected to each other by the shared contact trench. The shared contact trench includes a first silicide contact layer disposed on the first source/drain layer, and a second silicide contact layer disposed on the second source/drain layer, wherein the first and second silicide contact layers comprise different silicide materials, and a metallic fill layer disposed on the first and second silicide contact layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.