Integrated circuit products with gate structures positioned above elevated isolation structures
US10566328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Feb 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.