Nanosheet FET with box isolation on substrate
US10573755B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Sep 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a nanosheet semiconductor device includes depositing sacrificial material on a layer of silicon germanium (SiGe) above a substrate. A thickness of the sacrificial material is more than a thickness of the layer of SiGe. The method also includes forming nanosheet fins comprising alternating silicon (Si) nanosheets and silicon germanium (SiGe) layers on the sacrificial material, undercutting the SiGe layers to form divots, and forming a dummy gate structure above each of the nanosheet fins. A first liner is deposited to fill the divots and cover the nanosheet fins and the dummy gate structure. The sacrificial material and the first liner material are removed. The method also includes encapsulating the nanosheet fins and the dummy gate structure with a conformal liner, and performing an oxide fill to create a buried oxide (BOX) isolation between subsequently formed source and drain regions between the nanosheet fins and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.