Patent · US Active

Processor power management

US10579121B2 · kind B2 · utility

1Cited by

4References

14Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Altug Koker · Cameron Park, US
Abhishek R. Appu · Cameron Park, US
Kiran C. Veernapu · Kanchinakote, IN
Joydeep Ray · Folsom, US
Balaji Vembu · Folsom, US
Prasoonkumar Surti · Folsom, US
Kamal Sinha · Rancho Cordova, US
Eric J. Hoekstra · Holland, US
Wenyin Fu · Folsom, US
Nikos Kaburlasos · Lincoln, US
Bhushan M. Borole · Rancho Cordova, US
Travis T. Schluessler · Hillsboro, US
Ankur N. Shah · Folsom, US
Jonathan Kennedy · Bristol, GB

Key dates

Filing date	Apr 1, 2017
Grant date	Mar 3, 2020
Priority date	—
Expiry date	Apr 1, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D30/70
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.