Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same
US10580684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Apr 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.