FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
US10580867B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Nov 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.