Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

US10586860B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jiehui Shu · Clifton Park, US
• Laertis Economikos · Hopewell Junction, US
• Xusheng Wu · Hsinchu, TW
• John H. Zhang · Fishkill, US
• Haigou Huang · Rexford, US
• Hui Zhan · Shanghai, CN
• Tao Han · Nanjing, CN
• Haiting Wang · Clifton Park, US
• Jinping Liu · Ballston Lake, US
• Hui Zang · Guilderland, US

Key dates

• Filing date: May 3, 2018
• Grant date: Mar 10, 2020
• Expiry date: May 3, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.