Charge-scaling multiplier circuit
US10592209B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of two received binary numbers. The multiplier circuit includes two sets of inputs that receive binary numbers. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of an AND gate and to a local product output node. Each AND gate is connected to a unique pair of bits, one bit from each of the two binary numbers. Each scaled capacitor has a capacitance proportional to a product term generated by the corresponding AND gate. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.