Nanosheet transistors with sharp junctions
US10600638B2 · kind B2 · utility
3Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2016 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Oct 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.