SiN spacer profile patterning
US10600639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Jul 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon nitride surface on a semiconductor substrate within a processing region of a semiconductor processing chamber. The methods may include forming an inert plasma within the processing region of the processing chamber. Effluents of the inert plasma may be utilized to modify the oxidized silicon nitride. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified oxidized silicon nitride from the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.