Wafer and method for processing a wafer
US10600701B2 · kind B2 · utility
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1References
20Claims
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Key dates
| Filing date | Sep 4, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Sep 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68336
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.