Twin bit non-volatile memory cells with floating gates in substrate trenches
US10600794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Oct 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.