Method of forming gate of semiconductor device and semiconductor device having same

US10607896B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Lars-Ake Ragnarsson · New York, US
• Hendrik F.W. Dekkers · Tienen, BE
• Tom Schram · Rixensart, BE
• Julien Ryckaert · Schaerbeek - Schaarbeek, BE
• Naoto Horiguchi · Leuven, BE
• Mustafa Badaroglu · Kessel-Lo, BE

Key dates

• Filing date: May 10, 2017
• Grant date: Mar 31, 2020
• Expiry date: May 10, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first tren…