Controlling via critical dimension during fabrication of a semiconductor wafer
US10607922B1 · kind B1 · utility
3Cited by
14References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Oct 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.