Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10608043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2017 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Dec 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack. The readout circuitry may include a plurality of transistors each including spaced apart source and drain regions, a superlattice channel extending between the source and drain regions, and a gate including a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.