Variable latency pipe for interleaving instruction tags in a microprocessor
US10613868B2 · kind B2 · utility
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3References
11Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jan 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques disclosed herein describe a variable latency pipe for interleaving instruction tags in a processor. According to one embodiment presented herein, an instruction tag is associated with an instruction upon issue of the instruction from the issue queue. One of a plurality of positions in the latency pipe is determined. The pipe stores one or more instruction tags, each associated with a respective instruction. The pipe also stores the instruction tags in a respective position based on the latency of each respective instruction. The instruction tag is stored at the determined position in the pipe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.