Merging level cache and data cache units having indicator bits related to speculative execution
US10621092B2 · kind B2 · utility
1Cited by
78References
20Claims
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Key dates
| Filing date | Dec 8, 2014 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Mar 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.