Two-stage ramp up of word line voltages in memory device to suppress read disturb
US10629272B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Feb 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing read disturb of memory cells. A discharge process reduces a channel gradient in a NAND string by using a two-step ramp up of adjacent word lines of the selected word line. The voltages of the adjacent word lines can be provided at an intermediate level while the selected word line voltage is spiked up to a read pass voltage and then decreased. The voltages of the adjacent word lines can then be increased from the intermediate level to a read pass voltage and maintained at that level during the sensing of the memory cells. The voltage of the selected word line is decreased from a read pass voltage to a positive control gate read voltage at the end of the discharge process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.