Managing bit-line settling time in non-volatile memory
US10636498B1 · kind B1 · utility
13Cited by
10References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 22, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory system comprises a plurality of word lines, a plurality of bit lines, non-volatile memory cells, and a sensing circuit. The sensing circuit is configured to sense a first set of the memory cells coupled to a contiguous set of the bit lines and a selected word line using a first bit line settling time. The sensing circuit is configured to sense a second set of the memory cells coupled to a non-contiguous set of the bit lines and the selected word line using a second bit line settling time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.