Reducing read disturb in two-tier memory device by modifying ramp up rate of word line voltages during channel discharge
US10636500B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. The discharge involves ramping up the word line voltages and grounding the ends of the NAND strings. To increase the discharge, a ramp up rate may be greater for the selected word line and for dummy memory cells adjacent to the interface, compared to the ramp up rate for the unselected word lines. In an option, the greater ramp up rate is also used for the word lines between the selected word line and the interface. In another option, the greater ramp up rate is used for the word lines in the same tier as the selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.