Deep EPI enabled by backside reveal for stress enhancement and contact

US10636907B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Stephen M. Cea · Hillsboro, US
• Rishabh Mehandru · Portland, US
• Patrick Morrow · Portland, US
• Patrick H. Keys · Portland, US

Key dates

• Filing date: Sep 25, 2015
• Grant date: Apr 28, 2020
• Expiry date: Sep 25, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.