Patent · US Active

Low voltage, master-slave flip-flop

US10637447B2 · kind B2 · utility

0Cited by

2References

19Claims

0Family size

Inventors

Alok Tripathi · Beaverton, US
Amit Verma · Schweinhub, DE
Anuj Grover · New Delhi, IN
Deepak Kumar Bihani · Noida, IN
Tanmoy Roy · Mountain View, US
Tanuj Agrawal · Noida, IN

Key dates

Filing date	Mar 7, 2019
Grant date	Apr 28, 2020
Priority date	—
Expiry date	Mar 7, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.