Low profile integrated package
US10651160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jan 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package that includes a substrate comprising an interposer interconnect and a cavity, a redistribution portion coupled to the substrate, the redistribution comprising a plurality of redistribution interconnects, and a first die coupled to the redistribution portion through the cavity of the substrate. A substantial region between a side surface of the first die and the substrate is free of an encapsulation layer. In some implementations, the substrate is free of a metal ring that surrounds the first die. In some implementations, the redistribution portion comprises a barrier layer and a first interconnect coupled to the barrier layer. The barrier layer is coupled to the interposer interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.