FinFET structure and fabricating method of gate structure

US10651174B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Yi-Liang Ye
• Kuang-Hsiu Chen · Tainan, TW
• Chun-Wei Yu · Tainan, TW
• Chueh-Yang Liu · Dayton, US
• Yu-Ren Wang · Tainan, TW

Key dates

• Filing date: May 14, 2019
• Grant date: May 12, 2020
• Expiry date: May 14, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.