Memory device and forming method thereof
US10651193B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jul 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.