Patent · US Active

3D circuit transistors with flipped gate

US10651202B2 · kind B2 · utility

0Cited by

1References

12Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Francois Andrieu · Meylan, FR
Perrine Batude · Dijon, FR
Maud Vinet · Voiron, FR

Key dates

Filing date	Nov 20, 2018
Grant date	May 12, 2020
Priority date	—
Expiry date	Nov 20, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/85
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.