Memory system with dynamic calibration using a variable adjustment mechanism
US10664194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2018 |
| Grant date | May 26, 2020 |
| Priority date | — |
| Expiry date | Jun 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a processing device configured to iteratively determine a set of read results based on reading a subset of memory cells according to a set of read levels determine an update direction based on the set of read results, wherein the update direction corresponds to one of the set of read levels; determine whether a change condition is met; generate an updated read level for the set of read levels based on applying an adjustment step to one of the read levels in the set of read levels along the update direction, wherein the adjustment step is: a first step size in response to the change condition not being met, and a second step size in response to the change condition being met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.