Integrated structures and methods of forming vertically-stacked memory cells

US10665599B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Hongbin Zhu · Boise, US
• Gordon A. Haller · Boise, US
• Charles H. Dennison · San Jose, US
• Anish A. Khandekar · Boise, US
• Brett D. Lowe · Boise, US
• Lining He · Singapore, SG
• Brian Cleereman · Boise, US

Key dates

• Filing date: Apr 1, 2019
• Grant date: May 26, 2020
• Expiry date: Apr 1, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/35

Abstract

Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.