Charge-scaling multiplier circuit with dual scaled capacitor sets
US10671348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Nov 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.