Method of making fully molded peripheral package on package device
US10672624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2018 |
| Grant date | Jun 2, 2020 |
| Priority date | — |
| Expiry date | Jul 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.