Reducing read disturb in two-tier memory device by modifying duration of channel discharge based on selected word line
US10685723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. A discharge period is set based on a position of the selected word line in a stack or block of memory cells. The discharge period is longer when the selected word line is in the lower tier than in the upper tier. Additionally, the discharge period is longer when the selected word line is at a top of the lower tier than at a bottom of the lower tier. Other options to increase the discharge include increasing a ramp up rate and a peak level of the word line voltages during the discharge period as a function of the position of the selected word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.