Three-dimensional memory device with drain-select-level isolation structures and method of making the same
US10685979B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Feb 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electrical isolation between adjacent stripes of drain-select-level electrically conductive layers can be provided by forming a drain-select-level isolation structure between neighboring rows of memory stack structures. The drain-select-level isolation structure can partially cut through upper regions of the neighboring rows of memory stack structures. Vertical semiconductor channels of the neighboring rows of memory stack structures include a lower tubular segment and an upper semi-tubular segment that contact the drain-select-level isolation structure. Electrical current through drain select levels is limited to the semi-tubular segment of each vertical semiconductor channel. Alternatively, the drain-select-level isolation structure can be formed around the memory stack structures within the neighboring rows of memory stack structures. Ion implantation can be used to suppress conduction of electrical current through portions of vertical semiconductor channels that are proximal to the drain-select-level isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.