Methods for manufacturing an interconnect structure for semiconductor devices
US10692759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Jul 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.