Neural network classifier using array of two-gate non-volatile memory cells
US10699779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Apr 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neural network device having a first plurality of synapses that includes a plurality of memory cells. Each memory cell includes a floating gate over a first portion of a channel region and a first gate over a second portion of the channel region. The memory cells are arranged in rows and columns. A plurality of first lines each electrically connect together the first gates in one of the memory cell rows, a plurality of second lines each electrically connect together the source regions in one of the memory cell rows, and a plurality of third lines each electrically connect together the drain regions in one of the memory cell columns. The first plurality of synapses receives a first plurality of inputs as electrical voltages on the plurality of third lines, and provides a first plurality of outputs as electrical currents on the plurality of second lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.