Steven Lemke
42Patents
5h-index
21Co-inventors
65Inventor score
Filing activity: Feb 25, 2014 → Apr 24, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10748630B2 | High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks | Physics | 16 | Active |
| US10720217B1 | Memory device and method for varying program state separation based upon frequency of use | Electricity | 11 | Active |
| US10803943B2 | Neural network classifier using array of four-gate non-volatile memory cells | Electricity | 5 | Active |
| US11270771B2 | Neural network classifier using array of stacked gate non-volatile memory cells | Electricity | 5 | Active |
| US11270763B2 | Neural network classifier using array of three-gate non-volatile memory cells | Physics | 5 | Active |
| US11393546B2 | Testing circuitry and methods for analog neural memory in artificial neural network | Physics | 3 | Active |
| US10699779B2 | Neural network classifier using array of two-gate non-volatile memory cells | Physics | 3 | Active |
| US11482530B2 | Precision tuning for the programming of analog neural memory in a deep learning artificial neural network | Electricity | 3 | Active |
| US9275748B2 | Low leakage, low threshold voltage, split-gate flash cell operation | Electricity | 2 | Active |
| US10755783B2 | Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network | Physics | 2 | Active |
| US10741568B2 | Precision tuning for the programming of analog neural memory in a deep learning artificial neural network | Electricity | 2 | Active |
| US11636322B2 | Precise data tuning method and apparatus for analog neural memory in an artificial neural network | Physics | 1 | Active |
| US10790292B2 | Method of making embedded memory device with silicon-on-insulator substrate | Electricity | 1 | Active |
| US11682459B2 | Analog neural memory array in artificial neural network comprising logical cells and improved programming mechanism | Physics | 1 | Active |
| US11521682B2 | Temperature compensation in an analog memory array by changing a threshold voltage of a selected memory cell in the array | Physics | 1 | Active |
| US11646075B2 | Neural network classifier using array of three-gate non-volatile memory cells | Physics | 1 | Active |
| US12176039B2 | Setting levels for a programming operation in a neural network array | Physics | 0 | Active |
| US12124944B2 | Precise data tuning method and apparatus for analog neural memory in an artificial neural network | Physics | 0 | Active |
| US11683933B2 | Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network | General | 0 | Revoked |
| US12283314B2 | Neural network classifier using array of three-gate non-volatile memory cells | Physics | 0 | Active |
| US12056601B2 | Circuitry to compensate for data drift in analog neural memory in an artificial neural network | Physics | 0 | Active |
| US11847556B2 | Precise data tuning method and apparatus for analog neural memory in an artificial neural network | Physics | 0 | Active |
| US11183506B2 | Method of making embedded memory device with silicon-on-insulator substrate | Electricity | 0 | Active |
| US11783904B2 | Compensation for leakage in an array of analog neural memory cells in an artificial neural network | Physics | 0 | Active |
| US11362100B2 | FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.