Silicon die with integrated high voltage devices
US10700039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2014 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Jun 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.