Patent · US Active

Controlling coarse pixel size from a stencil buffer

US10706591B2 · kind B2 · utility

1Cited by

9References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Karthik Vaidyanathan · San Francisco, US
Prasoonkumar Surti · Folsom, US
Hugues Labbe · Folsom, US
Atsuo Kuwahara · Portland, US
Sameer Kp · Bengaluru, IN
Jonathan Kennedy · Bristol, GB
Murali Ramadoss · Folsom, US
Michael Apodaca · Folsom, US
Abhishek Venkatesh · Hillsboro, US

Key dates

Filing date	Sep 26, 2018
Grant date	Jul 7, 2020
Priority date	—
Expiry date	Sep 26, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06T2210/52
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.