Static random access memory
US10706914B2 · kind B2 · utility
5Cited by
8References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 26, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jun 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.