Source side program, method, and apparatus for 3D NAND
US10707226B1 · kind B1 · utility
4Cited by
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12Claims
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Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jun 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A source side programming method and system are provided. A bad trigger block, of a plurality of blocks of a memory array, may be detected by determining a threshold voltage distribution of a drain side select gate of a block and determining whether the distribution is abnormal. If the distribution is abnormal, the block is a bad trigger block which may cause a failure in another block. IF the block is a bad trigger block, source side programming is performed on at least one word line of the bad trigger block by applying a non-zero voltage to at least one source side word line of the bad trigger block via a source side line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.