Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same
US10707228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Feb 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/8182
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.