Formation of embedded magnetic random-access memory devices
US10707413B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Mar 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for fabricating magnetic random-access memory devices, which eliminate junction shorts and minimize gouging of an underlying insulating layer. For example, a bottom electrode layer, a magnetic tunnel junction (MTJ) stack, and an upper electrode layer are formed over an insulating layer. The bottom electrode layer and the MTJ stack are etched to form an upper electrode and a MTJ structure. A cleaning etch process removes residual metallic material which is re-deposited on sidewalls of the MTJ structure as a result of etching the MTJ stack. A conformal dielectric layer is formed to encapsulate the upper electrode and the MTJ structure and prevent oxidation or re-deposition of metallic material on the cleaned sidewalls of the MTJ structure. A final etch process is performed to pattern the conformal dielectric layer and bottom electrode layer to form a spacer on sidewalls of the MTJ structure and form a bottom electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.