Processors having virtually clustered cores and cache slices

US10725920B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Herbert Hum · Portland, US
• Brinda Ganesh · Portland, US
• James Vash · Littleton, US
• Ganesh Kumar · Sunnyvale, US
• Leena K. Puthiyedath · Beaverton, US
• Scott J. Erlanger · Boston, US
• Eric J. Dehaemer · Shrewsbury, US
• Adrian C. Moga · Portland, US
• Michelle M. Sebot · Haifa, IL
• Richard L. Carlson · Yakima, US
• David Bubien · Fort Collins, US
• Eric Delano · Fort Collins, US

Key dates

• Filing date: Apr 8, 2018
• Grant date: Jul 28, 2020
• Expiry date: Apr 8, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/084
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.