Manage source line bias to account for non-uniform resistance of memory cell source lines
US10726925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Oct 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for improving the reliability of data stored within a semiconductor memory are described. One issue with determining stored data states for memory cells within a NAND-type memory is that the voltage at the source end of a NAND string may vary greatly from when a memory cell of the NAND string is program verified to when the memory cell is subsequently read leading to bit errors. To compensate for this variability in the source line voltage, different sensing conditions (e.g., the bit line voltages and/or the sensing times) may be applied during a read operation to different sets of memory cells depending on the source line resistance from the memory cells or on the source line voltage zone assigned to the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.