Patent · US Active

Controlling back-end-of-line dimensions of semiconductor devices

US10727120B2 · kind B2 · utility

0Cited by

13References

14Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Sean Xuan Lin · Hopkins, US
Ruilong Xie · Niskayuna, US
Guoxiang Ning · Clifton Park, US
Lei Sun · Beijing, CN

Key dates

Filing date	Aug 23, 2018
Grant date	Jul 28, 2020
Priority date	—
Expiry date	Aug 23, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76829
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.