Thin film interconnects with large grains

US10727121B2 · kind B2 · utility

Assignee

• Elpis Technologies Inc. · CA

Inventors

• Robert L. Bruce · White Plains, US
• Cyril Cabral, Jr. · Ossining, US
• Gregory M. Fritz · Acton, US
• Eric A. Joseph · White Plains, US
• Michael F. Lofaro · Milton, US
• Hiroyuki Miyazoe · White Plains, US
• Kenneth P. Rodbell · Sandy Hook, US
• Ghavam G. Shahidi · Pound Ridge, US

Key dates

• Filing date: Nov 27, 2018
• Grant date: Jul 28, 2020
• Expiry date: Nov 27, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.