Patent · US Active

Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same

US10727208B2 · kind B2 · utility

1Cited by

0References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zhicheng Ding · Shanghai, CN
Bin Liu · Fishers, US
Yong She · Shanghai, CN
Aiping Tan · Shanghai, CN
Li Deng · Shanghai, CN

Key dates

Filing date	Sep 29, 2016
Grant date	Jul 28, 2020
Priority date	—
Expiry date	Sep 29, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19105
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.