Patent · US Active

Nanosheet transistor

US10727315B2 · kind B2 · utility

6Cited by

4References

9Claims

0Family size

Assignee

TESSERA LLC · US

Inventors

Kangguo Cheng · Schenectady, US
Juntao Li · Cohoes, US
Heng Wu · Guilderland, US
Peng Xu · Guilderland, US

Key dates

Filing date	Jan 20, 2019
Grant date	Jul 28, 2020
Priority date	—
Expiry date	Jan 31, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/018
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.