FinFET with high-k spacer and self-aligned contact capping layer
US10734233B2 · kind B2 · utility
3Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2018 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Feb 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.