Patent · US Active

Core for a data processing engine in an integrated circuit

US10747531B1 · kind B1 · utility

1Cited by

37References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Jan Langer · Chemnitz, DE
Baris Ozgul · Dublin, IE
Juan J. Noguera Serra · San Jose, US
Goran H K Bilski · Mölndal, SE
Tim Tuan · San Jose, US

Key dates

Filing date	Apr 3, 2018
Grant date	Aug 18, 2020
Priority date	—
Expiry date	Jul 24, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/8084
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.